AM29LVI16D datasheet(18/44 Pages) AMD

18 / 44 page

Am29LV116D

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 9 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence resets

the device to reading array data.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See “Erase Sus-

pend/Erase Resume Commands” for more information

on this mode.

The system

must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Figure 13 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 9 shows the address and data requirements. This

method is an alternative to that shown in Table 4, which

is intended for PROM programmers and requires VID

on address bit A9.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect com-

mand. The device then enters the autoselect mode,

and the system may read at any address any number

of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h returns the

device code. A read cycle containing a sector address

(SA) and the address 02h returns 01h if that sector is

protected, or 00h if it is unprotected. Refer to Tables 2

and 3 for valid sector addresses.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Byte Program Command Sequence

The device programs one byte of data for each program

operation. The command sequence requires four bus

cycles, and is initiated by writing two unlock write cy-

cles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is

not required to provide further controls or tim-

ings. The device automatically generates the program

pulses and verifies the programmed cell margin. Table

9 shows the address and data requirements for the

byte program command sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7,

DQ6, or RY/BY#. See “Write Operation Status” for in-

formation on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The Byte Program command se-

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