Digital pulse compression module

CI F07 Dual Expander

October 15

CI F07 Dual Expander Revision A1

2 / 6

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Technical description

CI F07 functional block diagram is featured on Fig. 1.

Fig. 1 : CI F07 functional block diagram

Unit description.

The internal low noise system clock is locked on an external clock (derived from the RADAR system clock). For

proper operation, the clock should be a good quality clock, with a low phase noise close to the carrier.

CI F07 unit is provided with FPGA firmware loaded. Functions, and channels specifications (time dispersion,

bandwidth…) should be provided by customer; Rakon will customize the FPGA program to fulfill customer

requirements.

CI F07 unit continuously monitors internal power supply and FPGA program integrity. If voltage exceeds nominal

levels, or if FPGA program is corrupted, UNIT_OK_OUT output is deasserted, and LED is turned off. The

UNIT_OK_OUT output indicates the GO-NOGO state of the compressor.

Pulse expander channel description.

After each Trigger pulse, a chirp defined by the samples set selected by WFMSELx_IN is generated, and

presented to the DAC input to be translated into an analog signal. Trigger input have to be synchronized with

Clock input.

For better compatibility with old SAW based subsystems, an adjustable additional delay may be inserted.

Expander waveform is selected among 2 possible waveforms, using WFMSELx_IN input, as presented in Table 1.

Each time WFMSELx_IN signal changes, the new set of waveform samples will be active for the next trigger pulse.

Table 1 : Expander Waveform Selection

WFMSELx

Expander Waveform

0

Waveform 0 (TBD)

1

Waveform 1 (TBD)