AFE5804ZCF datasheet(6/63 Pages) TI1

6 / 63 page

AFE5804

SBOS442C

– JUNE 2008 – REVISED OCTOBER 2011

www.ti.com

DIGITAL CHARACTERISTICS

DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level

'0' or '1'. At CLOAD = 5pF

(1), I

OUT = 3.5mA

(2), R

LOAD = 100Ω

(2), and no internal termination, unless otherwise noted.

AFE5804

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS

High-level input voltage

1.4

3.3

Low-level input voltage

0.3

High-level input current

μA

Low-level input current(3)

–10

μA

Input capacitance

LVDS OUTPUTS

High-level output voltage

1375

Low-level output voltage

1025

Output differential voltage, |VOD|

350

VOS output offset voltage

(2)

Common-mode voltage of OUTP and OUTM

1200

Output capacitance inside the device, from either

Output capacitance

output to ground

1x (clock

FCLKP and FCLKM

MHz

rate)

6x (clock

LCLKP and LCLKM

300

MHz

rate)

CLOCK

Clock input rate

MSPS

Clock duty cycle

Clock input amplitude, differential

Sine-wave, ac-coupled

VPP

(VCLKP

– VCLKM)

LVPECL, ac-coupled

1.6

VPP

LVDS, ac-coupled

0.7

VPP

Clock input amplitude, single-ended

(VCLKP)

High-level input voltage, VIH

CMOS

2.2

Low-level input voltage, VIL

CMOS

0.6

(1)

CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(2)

IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(3)

Except pin J3 (INT/EXT), which has an internal pull-up resistor (52k

Ω) to 3.3V.

AFE5804ZCF Scheda tecnica(PDF) 6 Page - Texas Instruments

AFE5804ZCF Scheda tecnica(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Scheda tecnica Scarica

Link URL