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8

Data Parity Detected —This bit is set when:

1) The PC87200 asserted PERR# or observed PERR# asserted.

2) PC87200 is the master for the cycle in which the PERR# occurred, and PE is set (F0 Index 04h[6] = 1).

Write 1 to clear.

7

Fast Back-to-Back Capable — As a target, PC87200 is capable of accepting fast back-to-back transactions:

0 = Disable; 1 = Enable. This bit is always set to 1.

6:0

Reserved — Set to 0.

Index 08h

Device Revision ID Register (RO)

Reset Value = 00h

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 060100h

Index 0Ch

PCI Cache Line Size Register (R/W)

Reset Value = 00h

7:0

PCI Cache Line Size Register — reserved.

Index 0Dh

PCI Latency Timer Register (R/W)

Reset Value = 00h

7:4

Reserved — Set to 0.

3:0

PCI Latency Timer Value — The PCI Latency Timer Register prevents system lockup when a slave does not

respond to a cycle that the PC87200 masters. If the value is set to 00h (default), the timer is disabled. If the

timer is written with any other value, bits [3:0] become the four most significant bytes in a timer that counts

PCI clocks for slave response. The timer is reset on each valid data transfer. If the counter expires before the

next assertion of TRDY# is received, the PC87200 stops the transaction with a master abort and asserts

SERR#, if enabled to do so.

Index 0Eh

PCI Header Type (RO)

Reset Value =00h

7:0

PCI Header Type Register — This.register defines the format of this header. This header is of type format 0.

Additionally, bit 7 defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0).

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

7:0

Reserved. Set to 0.

Index 10h-3Fh

Reserved

Reset Value = 00h

Index 40h

PCI Function Control Register 1 (R/W)

Reset Value = 79h

7

Internal use, do not overwrite.

6

Single Write Mode — PC87200 accepts only single cycle write transfers as a slave on the PCI bus and per-

forms a target disconnect with the first data transferred: 0 = Disable (accepts burst write cycles); 1 = Enable.

5

Single Read Mode — PC87200 accepts only single cycle read transfers as a slave on the PCI bus and per-

forms a target disconnect with the first data transferred. 0 = Disable (accepts burst read cycles); 1 = Enable.

4

Retry PCI Cycles — Retry inbound PCI cycles if data is buffered and waiting to go outbound on PCI:

0 = No Retry; 1 = Retry.

3

Write Buffer — PCI slave write buffer: 0 = Disable; 1 = Enable.

2:1

Reserved- set to 0.

0

BS8/16 — This bit can not be written. Always = 1.

Note: Bits 6 and 5 emulate the behavior of first generation devices developed for PCI.

Table 4. Bridge Configuration Registers (Continued)

Bit

Description