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SN65LVDS2DBVT Scheda tecnica(PDF) 31 Page - Texas Instruments |
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SN65LVDS2DBVT Scheda tecnica(HTML) 31 Page - Texas Instruments |
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31 / 42 page ![]() SN65LVDS1, SN65LVDS2, SN65LVDT2 www.ti.com SLLS373L – JULY 1999 – REVISED DECEMBER 2014 Layout Example (continued) Short and low-impedance connection of the device ground pins to the PCB ground plane reduces ground bounce. Holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas. To minimize EMI problems, TI recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. Zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues. Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: SN65LVDS1 SN65LVDS2 SN65LVDT2 |
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