LED6000 datasheet(30/49 Pages) STMICROELECTRONICS

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Application notes - step-down conversion

LED6000

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DocID027777 Rev 2

parasitic capacitance of the board, the RF required value is computed by Equation 21.



Select CF in order to place FZ1 below FLC (typically 0.1 * FLC)



Select CP in order to place FP1 at 0.5 * FSW

Equation 22

The resultant control loop and other transfer functions gain are shown in Figure 18.

Figure 18. Type II compensation - Bode plot

5.4

Thermal considerations

The thermal design is important to prevent the thermal shutdown of the device if junction

temperature goes above 170 °C (typ.). The three different sources of losses within the

device are:



Conduction losses due to the non-negligible RDSON of the power switch; these are

equal to:

Equation 23

where D is the duty cycle of the application and the maximum RDSON, over the temperature,

is 420 m

. Note that the duty cycle is theoretically given by the ratio between VOUT and

VIN, but actually it is slightly higher in order to compensate the losses of the regulator. So

the conduction losses increase compared with the ideal case.



Switching losses due to power MOSFET turn ON and OFF; these can be calculated as:









;



2

OUT





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