PC97338VLJ datasheet(45/221 Pages) NSC

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2.3.2

Function Enable Register (FER),

Index 00h

This register enables and disables major chip func-

tions. Disabled functions have their clocks automati-

cally powered down, but the data in their registers

remains intact. It also selects whether the FDC con-

troller is located at the primary or secondary address.

FIGURE 3. FER Register Bitmap

Bit 0 - Parallel Port Enable

0 - The parallel port is disabled.

1 - The parallel port can be accessed at the ad-

dress specified by: In Legacy mode: the FAR

bits 1,0. In Plug and Play mode: by PBAL and

PBAH registers.

Bit 1- SCC1 Enable

This bit enables or disables SCC1.

Any SCC1 interrupt that is enabled and active, or

becomes active after SCC1 is disabled, asserts

the associated IRQ pin when SCC1 is disabled. If

disabling SCC1 via software, clear ISEN bit (see

sec. 5.14.5 on page 159) to 0 before clearing FER

bit 1. This is not an issue after reset because ISEN

is 0 until it is written.

0 - Access to SCC1 is blocked and it is in power

down mode. The SCC1 registers retain all

data in power down mode.

Select MSEN1, DRATE1, CS0 or SIRQI2

Select DRV2, DR23, PNF or SIRQI3

543

Reset

Required

(SIRQ2)

System IRQ Input 2

Index 4Dh

Configuration Register

Invert SIRQI2

SIRQI2 Status

SIRQI2 Mapping

543

Reset

Required

(SIRQ3)

System IRQ Input 3

Index 4Eh

Configuration Register

Invert SIRQI3

SIRQI3 Status

SIRQI3 Mapping

SCC2 DMA

SCC2 DMA Plug and Play

Reserved

543

Reset

Required

(PNP3)

Plug and Play Configuration

Index 4Fh

Plug and Play Support

for Reception

Reserved

Support for Transmission

543

Reset

Required

Index 50h

SuperI/O Configuration

Select DRATE, MSEN1,

Select DRV2, PNF, DR23,

Select IRQI2, IRRX2 or IRSL0

Select MTR1, IDLE or IRSL2

Reserved

CS0, SIRQI2 or DACK3

SIRQI3 or IRSL2

Reserved

543

Reset

Required

Index 51h

Clock Control

Reserved

Clock Multiplier Enable

Valid Clock Multiplier Status

Reserved

SuperI/O Chip

Clock Source

543

Reset

Required

Function Enable

Index 00h

Parallel Port Enable

SCC1 Enable

SCC2 Enable

FDC Enable

FDC Four-Drive Encoding

Select FDC Secondary Address

Reserved

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