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PC87366 Scheda tecnica(PDF) 185 Page - National Semiconductor (TI) |
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PC87366 Scheda tecnica(HTML) 185 Page - National Semiconductor (TI) |
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185 / 240 page ![]() 11.0 Voltage Level Monitor (VLM) (Continued) 185 www.national.com 11.5.5 Voltage Event to SMI Register 1 (VEVSMI1) This register is one of two registers that controls event routing to SMI. Location: Offset 03h Type: RW Bit 765432 1 0 Name Reserved TMS3 Event to SMI Enable TMS2 Event to SMI Enable TMS1 Event to SMI Enable AVDD Event to SMI Enable VBAT Event to SMI Enable VDD Event to SMI Enable Reset 0 00000 0 0 Bit Description 7-6 Reserved 5 TMS3 Event to SMI Enable 0: Disabled (default) 1: Enabled 4 TMS2 Event to SMI Enable 0: Disabled (default) 1: Enabled 3 TMS1 Event to SMI Enable 0: Disabled (default) 1: Enabled 2 AVDD Event to SMI Enable 0: Disabled (default) 1: Enabled 1 VBAT Event to SMI Enable 0: Disabled (default) 1: Enabled 0 VDD Event to SMI Enable 0: Disabled (default) 1: Enabled |
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