PC87570-ICCSLASHVUL datasheet(38/168 Pages) NSC

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Bus Interface Unit (BIU)

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3.3.4

Late Write Bus Cycle

If the BCFG.EWR configuration bit is 0, the BIU uses the

late write bus cycle. The basic late write bus cycle takes two

clock cycles. This write bus cycle requires the RD signal in

the memory device interface.

A write bus cycle starts at T1, when the data bus is in TRI-

STATE, the address is placed on the address bus and SELn

(or SELIO) is activated. Next, WR0-1 are activated; RD is

inactive to indicate this is a write transaction.

At the first TIW or T2 (when there is no TIW cycles), the data

is placed on the data bus. The bus cycle is completed at T2,

when WR0-1 deactivates; the address and data remain val-

id until T2 is completed.

After T2, the number of Thold cycles specified by SZCF-

Gn.HOLD (may be 0) are added. When Thold cycles are

added, the address and data remain valid until the end of

the last Thold cycle. SELn (or SELIO) is deactivated on the

first Thold cycle. When no Thold cycles are specified, SELn

(or SELIO) is deactivated in the clock cycle after T2, unless

another read or write from the same zone follows. The data

is put in TRI-STATE in the clock cycle after the last Thold or

T2 (if no Thold cycle is configured). See Figures 3-4, 3-5 and

3-6.

Hold cycles

according to

SZCFGn.HOLD

≠ 0

SZCFGn.WAIT

≠ 0

SZCFGn.WAIT = 0

First Thold

SELn inactive

Hold cycles completed

Address placed on A0-15

SELn: activated

WR0-1: activated

Data placed

on D0-15

Internal waits completed

SZCFGn.HOLD=0

Address on A0-15 invalid/changed

Data put in TRI-STATE

SELn inactive

Data placed on D0-15

WR0-1: inactive

Internal waits corresponding to SZCFGn.WAIT

Thold

TIW

end

begin

Note: Any reference to SZCFGn also applies to the IOCFG Register.

Figure 3-4. Late Write Bus Cycle

Any reference to SELn also applies to the SELIO signal.

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