A5975AD datasheet(13/50 Pages) STMICROELECTRONICS

13 / 50 page

A5975AD

Functional description

Doc ID 018761 Rev 1

13/50

The synchronization feature of a set of the A5975AD is simply obtained by connecting

together their SYNCH pins. The device with the highest switching frequency is the master

which provides the synchronization signal to the others. Therefore the SYNCH is an I/O pin

to deliver or recognize a frequency signal. The synchronization circuitry is powered by the

internal reference (VREF) so a small filtering capacitor (≥ 100 nF) connected between the

VREF pin and the signal ground of the master device is recommended for its proper

operation. However, when a set of synchronized devices populates a board it is not possible

to know in advance the one working as master, so the filtering capacitor must be designed

for a whole set of devices.

When one or more devices are synchronized to an external signal, its amplitude must be in

compliance with specifications given in Table 4. The frequency of the synchronization signal

must be, at a minimum, higher than the maximum guaranteed natural switching frequency of

the device (275 kHz, see Table 4) while the duty cycle of the synchronization signal can vary

from approximately 10% to 90%. The small capacitor under VREF pin is required for this

operation.

Figure 5.

Oscillator circuit block diagram

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