ST7DALIF2 datasheet(53/171 Pages) STMICROELECTRONICS

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ST7DALIF2

Power saving modes

53/171

Figure 23.

Halt mode timing overview

Figure 24.

Halt mode flowchart

WDGHALT is an option bit. See option byte section for more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 15: Interrupt mapping for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

If the PLL is enabled by option byte, it outputs the clock after a delay of tSTARTUP (see Figure 11).

HALT

RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[Active Halt disabled]

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

IBIT

OFF

X 4)

CPU

OSCILLATOR

PERIPHERALS

IBIT

X 4)

256 OR 4096 CPU CLOCK

DELAY5)

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

CYCLE

HALT INSTRUCTION

(Active-halt disabled)

(AWUCSR.AWUEN=0)

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