ST7LITEUS5 datasheet(81/136 Pages) STMICROELECTRONICS

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cycles) and the CADC sample capacitor is disconnected from the analog input pin to get

the optimum analog to digital conversion accuracy.

●

The total conversion time:

tCONV = tSAMPLE + tHOLD

While the ADC is on, these two phases are continuously repeated.

At the end of each conversion, the sample capacitor is kept loaded with the previous

measurement load. The advantage of this behavior is that it minimizes the current

consumption on the analog pin in case of single input channel measurement.

A/D conversion

The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the “I/O

ports” chapter. Using these pins as analog inputs does not affect the ability of the port to be

read as a logic input.

In the ADCCSR register, select the CS[2:0] bits to assign the analog channel to convert.

ADC conversion mode

In the ADCCSR register, set the ADON bit to enable the A/D converter and to start the

conversion. From this time on, the ADC performs a continuous conversion of the selected

channel. When a conversion is complete:

●

The EOC bit is set by hardware.

●

The result is in the ADCDR registers.

A read to the ADCDRH resets the EOC bit.

To read the 10 bits, perform the following steps:

Poll EOC bit

Read ADCDRL

Read ADCDRH. This clears EOC automatically.

To read only 8 bits, perform the following steps:

Poll EOC bit

Read ADCDRH. This clears EOC automatically.

10.3.4

Low power modes

The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced

power consumption when no conversion is needed and between single shot conversions.

Table 31.

Effect of low power modes

Mode

Description

Wait

No effect on A/D converter

Halt

A/D converter disabled.

After wakeup from Halt mode, the A/D converter requires a stabilization time

tSTAB (see Section 12: Electrical characteristics) before accurate conversions

can be performed.

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