STM32L432KB datasheet(19/149 Pages) STMICROELECTRONICS

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STM32L432KB STM3L432KC

Functional overview

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

•

Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the low-

power run mode.

•

Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI

RC and the HSI16 RC are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode

to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,

most of the VCORE domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller

wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator

remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI

up to 48 MHz or HSI16, depending on software configuration.

•

Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The

internal regulator is switched off so that the VCORE domain is powered off. The PLL,

the MSI RC and the HSI16 RC are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers

in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in

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