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AD1833AAST Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte AD1833AAST
Spiegazioni elettronici  24-Bit, 192 kHz, DAC
PDF  20 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD1833AAST Scheda tecnica(HTML) 6 Page - Analog Devices

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AD1833A
–6–
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
OUTRP1
OUTRN1
AVDD
AVDD
AGND
AGND
AGND
OUTLP1
OUTLN1
AVDD
AVDD
AGND
AGND
AGND
DGND
DVDD1
ZEROA
ZERO3R
DGND
DVDD2
RESET
ZERO1L
AD1833A
ZERO3L
ZERO1R
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic IN/OUT
Description
1
OUTLP1
O
DAC 1 Left Channel Positive Output.
2
OUTLN1
O
DAC 1 Left Channel Negative Output.
3, 4, 33, 34, 44
AVDD
Analog Supply.
5, 6, 7, 30, 31, 32, 41
AGND
Analog Ground.
8, 29
DGND
Digital Ground.
9DVDD1
Digital Supply to Core Logic.
10
ZEROA
O
Flag to Indicate Zero Input on All Channels.
11
ZERO3R
O
Flag to Indicate Zero Input on Channel 3 Right.
12
ZERO3L
O
Flag to Indicate Zero Input on Channel 3 Left.
13
ZERO2R
O
Flag to Indicate Zero Input on Channel 2 Right.
14
CLATCH
I
Latch Input for Control Data (SPI Port).
15
CDATA
I
Serial Control Data Input (SPI Port).
16
CCLK
I
Clock Input for Control Data (SPI Port).
17
L/RCLK
I/O
Left/Right Clock for DAC Data Input; FSTDM Input in TDM Slave Mode;
FSTDM Output in TDM Master Mode.
18
BCLK
I/O
Bit Clock for DAC Data Input; BCLKTDM Input in TDM Slave Mode; BCLKTDM
Output in TDM Master Mode.
19
MCLK
I
Master Clock Input.
20
SDIN1I
Data Input for Channel 1 Left/Right (Data Stream Input in TDM and Packed Modes).
21
SDIN2
I/O
Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary DAC in
TDM Mode).
22
SDIN3
I/O
Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary DAC in TDM Mode).
23
SOUT
O
Auxiliary I
2S Output (Available in TDM Mode).
24
ZERO2L
O
Flag to Indicate Zero Input on Channel 2 Left.
25
ZERO1R
O
Flag to Indicate Zero Input on Channel 1 Right.
26
ZERO1L
O
Flag to Indicate Zero Input on Channel 1 Left.
27
RESET
IPower-Down and Reset Control.
28
DVDD2
Power Supply to Output Interface Logic.
35
OUTRN1
O
DAC 1 Right Channel Negative Output.
36
OUTRP1
O
DAC 1 Right Channel Positive Output.
37
OUTRN2
O
DAC 2 Right Channel Negative Output.
38
OUTRP2
O
DAC 2 Right Channel Positive Output.
39
OUTRN3
O
DAC 3 Right Channel Negative Output.



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