MX66L51235FZ2I-10G datasheet(4/83 Pages) MCNIX

4 / 83 page

MX66L51235F

Rev. 1.1, August 02, 2016

P/N: PM1832

Figures

Figure 1. Serial Modes Supported ...............................................................................................................................................13

Figure 2. Serial Input Timing........................................................................................................................................................14

Figure 3. Output Timing ...............................................................................................................................................................14

Figure 4. EAR Operation Segments ............................................................................................................................................16

Figure 5. Enable QPI Sequence ..................................................................................................................................................17

Figure 6. Reset QPI Mode ...........................................................................................................................................................17

Figure 7. Write Enable (WREN) Sequence (SPI Mode) ..............................................................................................................23

Figure 8. Write Enable (WREN) Sequence (QPI Mode)..............................................................................................................23

Figure 9. Write Disable (WRDI) Sequence (SPI Mode)...............................................................................................................24

Figure 10. Write Disable (WRDI) Sequence (QPI Mode).............................................................................................................25

Figure 11. Read Identification (RDID) Sequence (SPI mode only)..............................................................................................25

Figure 12. Read Electronic Signature (RES) Sequence (SPI Mode)...........................................................................................26

Figure 13. Read Electronic Signature (RES) Sequence (QPI Mode) .........................................................................................27

Figure 14. Release from Deep Power-down (RDP) Sequence (SPI Mode) ................................................................................27

Figure 15. Release from Deep Power-down (RDP) Sequence (QPI Mode)................................................................................27

Figure 16. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only) ......................................................28

Figure 17. Read Status Register (RDSR) Sequence (SPI Mode) ...............................................................................................30

Figure 18. Read Status Register (RDSR) Sequence (QPI Mode) ...............................................................................................30

Figure 19. Read Configuration Register (RDCR) Sequence (SPI Mode) ....................................................................................31

Figure 20. Read Configuration Register (RDCR) Sequence (QPI Mode)....................................................................................31

Figure 21. Program/Erase flow with read array data ...................................................................................................................32

Figure 22. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag) ...................................................................33

Figure 23. Write Status Register (WRSR) Sequence (SPI Mode)..............................................................................................37

Figure 24. Write Status Register (WRSR) Sequence (QPI Mode)..............................................................................................37

Figure 25. WRSR flow .................................................................................................................................................................39

Figure 26. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ..........................................................................40

Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only) ...............................................................................................42

Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI Mode) ...................................................................................43

Figure 29. Dual Read Mode Sequence .......................................................................................................................................44

Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only) .........................................................................................................45

Figure 31. Quad Read Mode Sequence ......................................................................................................................................46

Figure 32. 4 x I/O Read Mode Sequence (SPI Mode) .................................................................................................................48

Figure 33. 4 x I/O Read Mode Sequence (QPI Mode).................................................................................................................48

Figure 34. Read Data Bytes using 4 Byte Address Sequence (READ4B)...................................................................................49

Figure 35. Read Data Bytes at Higher Speed using 4 Byte Address Sequence (FASTREAD4B)...............................................49

Figure 36. 2 x I/O Fast Read using 4 Byte Address Sequence (2READ4B)................................................................................50

Figure 37. 4 I/O Fast Read using 4 Byte Address sequence (4READ4B) ...................................................................................50

Figure 38. SPI Mode....................................................................................................................................................................51

Figure 39. QPI Mode ...................................................................................................................................................................51

Figure 40. 4 x I/O Read performance enhance Mode Sequence (SPI Mode) ............................................................................53

Figure 41. 4 x I/O Read performance enhance Mode Sequence (QPI Mode) ............................................................................54

Figure 42. Fast Boot Sequence (QE Bit=0) .................................................................................................................................56

Figure 43. Fast Boot Sequence (QE Bit=1) .................................................................................................................................56

Figure 44. Read Fast Boot Register (RDFBR) Sequence ...........................................................................................................57

Figure 45. Write Fast Boot Register (WRFBR) Sequence...........................................................................................................57

Figure 46. Erase Fast Boot Register (ESFBR) Sequence...........................................................................................................57

Figure 47. Sector Erase (SE) Sequence (SPI Mode) ..................................................................................................................58

Figure 48. Sector Erase (SE) Sequence (QPI Mode)..................................................................................................................58

Figure 49. Block Erase 32KB (BE32K) Sequence (SPI Mode)....................................................................................................59

Figure 50. Block Erase 32KB (BE32K) Sequence (QPI Mode) ...................................................................................................59

Figure 51. Block Erase (BE) Sequence (SPI Mode)....................................................................................................................60

Figure 52. Block Erase (BE) Sequence (QPI Mode) ...................................................................................................................60

Figure 53. Chip Erase (CE) Sequence (SPI Mode) .....................................................................................................................61

Figure 54. Chip Erase (CE) Sequence (QPI Mode).....................................................................................................................61

Figure 55. Page Program (PP) Sequence (SPI Mode)................................................................................................................63

Figure 56. Page Program (PP) Sequence (QPI Mode) ...............................................................................................................63

Figure 57. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)...........................................................................................64

Figure 58. Deep Power-down (DP) Sequence (SPI Mode) .........................................................................................................65

Figure 59. Deep Power-down (DP) Sequence (QPI Mode)........................................................................................................65

Figure 60. WPSEL Flow...............................................................................................................................................................69

Figure 61. Advanced Sector Protection Overview .......................................................................................................................70

Figure 63. Read Lock Register (RDLR) Sequence......................................................................................................................71

Figure 62. Write Lock Register (WRLR) Sequence (SPI Mode)..................................................................................................71

Figure 64. SPB Lock Bit Set (SPBLK) Sequence ........................................................................................................................72

Figure 65. Read SPB Lock Register (RDSPBLK) Sequence ......................................................................................................72

Figure 66. Read SPB Status (RDSPB) Sequence.......................................................................................................................74

Figure 67. SPB Erase (ESSPB) Sequence .................................................................................................................................74

Figure 68. SPB Program (WRSPB) Sequence............................................................................................................................74

Figure 69. Read DPB Register (RDDPB) Sequence ...................................................................................................................75

Figure 70. Write DPB Register (WRDPB) Sequence...................................................................................................................75

Figure 71. Suspend to Read Latency ..........................................................................................................................................79

Figure 72. Resume to Read Latency ...........................................................................................................................................79

Figure 73. Resume to Suspend Latency .....................................................................................................................................79

Figure 74. Software Reset Recovery...........................................................................................................................................81

Figure 75. Reset Sequence (SPI mode)......................................................................................................................................81

Figure 76. Reset Sequence (QPI mode) .....................................................................................................................................81

Figure 77. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence ............................................................................82

Figure 78. RESET Timing ............................................................................................................................................................88

Figure 79. Maximum Negative Overshoot Waveform..................................................................................................................90

Figure 80. Maximum Positive Overshoot Waveform....................................................................................................................90

Figure 81. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL .....................................................................................91

Figure 82. OUTPUT LOADING...................................................................................................................................................91

Figure 83. AC Timing at Device Power-Up ..................................................................................................................................94

Figure 84. Power-Down Sequence..............................................................................................................................................95

Figure 85. Power-up Timing.........................................................................................................................................................95

Figure 86. Power Up/Down and Voltage Drop.............................................................................................................................96

MX66L51235FZ2I-10G Scheda tecnica(PDF) 4 Page - Macronix International

MX66L51235FZ2I-10G Scheda tecnica(HTML) 4 Page - Macronix International

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Scheda tecnica Scarica

Link URL