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Z8FS021 Scheda tecnica(PDF) 30 Page - Zilog, Inc. |
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Z8FS021 Scheda tecnica(HTML) 30 Page - Zilog, Inc. |
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30 / 68 page ![]() PS028806-0315 PIR Engine and API ZMOTION® Intrusion Detection Product Specification 22 CPU Cycles: 261 Peripherals initialized: ADC and GPIO, depending on API-selected options. The ADC IRQ is set for medium priority. EPIR_ADC_ISR Macro. This macro is executed for each ADC conversion. The applica- tion handles the ADC interrupt and executes this macro. All motion detection processing is performed by this macro. EPIR_ADC_ISR Macro: PUSHX RP LDX RP, #%E0 CALL %1000 POPX RP The CPU cycles used by the EPIR_ADC_ISR macro vary depending on Engine state and configuration. PIR Engine CPU Stack Usage The PIR Engine shares the processor stack with the user application. There are no special requirements on the placement of the stack in memory, but it is essential that the user pro- vide enough stack space for both the user application and the PIR Engine. The PIR Engine requires a maximum 6 bytes of stack. |
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