TP3420AV datasheet(12/32 Pages) NSC

12 / 32 page

Functional Description (Continued)

TABLE 4. Control Register Functions (Continued)

Function

Mnemonic

Bit Number

76543210

Control Device State Reading

Disable the Device State Output on the NOCST (Note 6)

DISST

10010011

Control of Additional Interrupts

Enable the Slip and RMFE Interrupts

ENINT

10010100

Disable the Slip and RMFE Interrupts (Note 6)

DISINT

10010101

Control Polarity of B Channel Data

Invert B1 Channel Data

INVB1

10011101

Invert B2 Channel Data

INVB2

10011110

Normal B1, B2 Data (Note 6)

NRMB12

10011111

Pin Signal Selection

Redefine Pin Signals (See

Table 1)

PINDEF

11100

Note 6: Indicates initial state following Power-on initialization.

Note 7: Slave-slave mode.

Note 8: DACCD is the power up default in TES mode and DACCE is the power up default in TEM mode.

TABLE 5. Status Register Functions

Function

Mnemonic

Bit Number

6543210

Line Signal Detected Far-End

LSD

0000010

Activation Pending

0000011

Activation Indication

0001100

Error Indication

0001110

Deactivation Indication

0001111

End of D-ch Tx Message

EOM

0000110

Lost Contention for D-ch

CON

0000111

Multiframe Receiver Buffer 1 (SC1/Q)

MFR1

Multiframe Receiver Buffer 2 (SC2)

MFR2

Multiframe Clock (5 ms or 30 ms)

MFC

0000100

Additional Interrupts after ENINT Command

Receive Multiframe Error

RMFE

0000101

Phase Slip in Data Buffer for Bx Data

SLIP TX

0001001

Phase Slip in Data Buffer for Br Data

SLIP RX

0001010

Phase Slip for Both Bx and Br Data

SLIP TX/RX

0001011

NO Change Return Status

NOC Status after DISST Command (Note

NOC

0000000

NOC Status after ENST Command

NOCST

0000

See

Table 6 for Device State Decoding

Note 9: Indicates initial state following Power-on Initialization.

STATUS INDICATOR DESCRIPTIONS

LSD

This interrupt indicates that the far-end of the line

is attempting to Activate the interface. May be

used as an alternative to the LSD pin to “wake-up”

a microprocessor.

If set, indicates that either INFO 1 frames have

been identified in an NT receiver, or INFO 2 or

INFO 4 frames have been identified in a TE re-

ceiver. Requires an AR control instruction to allow

Activation to be completed.

EOM

This interrupt occurs when the closing flag of a

D-channel message has been transmitted by a TE

on the S interface, indicating successful comple-

tion of a packet. The Interrupt associated with this

bit can be disabled via the Control Register if de-

sired.

CON

This interrupt occurs when, during transmission of

TP3420AV Scheda tecnica(PDF) 12 Page - National Semiconductor (TI)

TP3420AV Scheda tecnica(HTML) 12 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Scheda tecnica Scarica

Link URL