Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

SPEAR600 Scheda tecnica(PDF) 42 Page - STMicroelectronics

Il numero della parte SPEAR600
Spiegazioni elettronici  Embedded MPU with dual ARM926 core, flexible memory support, powerful connectivity features and programmable LCD interface
PDF  97 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPEAR600 Scheda tecnica(HTML) 42 Page - STMicroelectronics

Back Button SPEAR600 Datasheet HTML 38Page - STMicroelectronics SPEAR600 Datasheet HTML 39Page - STMicroelectronics SPEAR600 Datasheet HTML 40Page - STMicroelectronics SPEAR600 Datasheet HTML 41Page - STMicroelectronics SPEAR600 Datasheet HTML 42Page - STMicroelectronics SPEAR600 Datasheet HTML 43Page - STMicroelectronics SPEAR600 Datasheet HTML 44Page - STMicroelectronics SPEAR600 Datasheet HTML 45Page - STMicroelectronics SPEAR600 Datasheet HTML 46Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 42 / 97 page
background image
Pin description
SPEAr600
42/97
Doc ID 16259 Rev 3
3.3.4
Disable GMAC ctr
The GMAC interface is disabled and alternatively the following features are provided:
Two UARTs : one with extension for modem flow control and one with simplified
hardware flow control
One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user
manual for more details).
Four additional clocks programmable trough the GPT registers. Please refer to the
SPEAr600 user manual (UM0510) for more details.
3.3.5
Self cfg_4
In this mode the AHB expansion interface is enabled on the PL_GPIO (83:0) pins. In this
mode source clock and reset signals are provided from the external application logic.
3.3.6
Self cfg_5
In this mode the AHB expansion interface is enabled on the PL_GPIO (83:0) pins. In this
mode source clock and reset signals are internally provided.
3.3.7
All processors disabled
This mode configures the SoC as an I/O slave target device controlled by an external master
application (the internal processors can be disabled).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com