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ESD8024 Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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ESD8024 Scheda tecnica(HTML) 2 Page - ON Semiconductor |
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2 / 6 page ![]() ESD8024 http://onsemi.com 2 See Application Note AND8308/D for further description of survivability specs. Pin 1 Pin 2 Pin 3 Pin 22 Pin 23 Pin 24 Center Pad Figure 1. Pin Schematic ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter VRWM Working Peak Voltage IR Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT IT Test Current VHOLD Holding Reverse Voltage IHOLD Holding Reverse Current RDYN Dynamic Resistance IPP Maximum Peak Pulse Current VC Clamping Voltage @ IPP VC = VHOLD + (IPP * RDYN) I V VCVRWMVHOLD VBR RDYN VC IR IT IHOLD −IPP RDYN IPP VC = VHOLD + (IPP * RDYN) ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage VRWM All Pins (1−24) to GND (Note 1) 2.5 V Forward Voltage VF IF = 10 mA, GND to All Pins (1−24) 0.5 0.85 1.1 V Breakdown Voltage VBR IT = 1 mA, All Pins (1−24) to GND 5.5 7.0 9.0 V Reverse Leakage Current IR VRWM = 2.5 V, All Pins (1−24) to GND 0.5 mA Holding Reverse Voltage VHOLD I/O Pin to GND 1 1.5 V Holding Reverse Current IHOLD I/O Pin to GND 50 mA Clamping Voltage VC IPP = 1 A, All Pins (1−24) to GND (8/20 ms pulse) 4.0 V Clamping Voltage VC IPP = 10 A, All Pins (1−24) to GND (8/20 ms pulse) 7.0 V Clamping Voltage VC IPP = 15 A, All Pins (1−24) to GND (8/20 ms pulse) 8.0 V Clamping Voltage VC IEC61000−4−2, ±8 kV Contact See Figures 2 and 3 V Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins 2.0 pF Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 4.0 pF 1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. |
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