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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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S128 Scheda tecnica(PDF) 59 Page - Renesas Technology Corp |
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S128 Scheda tecnica(HTML) 59 Page - Renesas Technology Corp |
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59 / 107 page  R01DS0309EU0100 Rev.1.00 Page 59 of 107 Mar 10, 2017 S128 2. Electrical Characteristics Figure 2.37 GPT input capture timing Figure 2.38 AGT I/O timing Figure 2.39 ADC14 trigger input timing Figure 2.40 Key interrupt input timing 2.3.7 PWM Delay Generation Circuit Timing Table 2.31 PWM delay generation circuit timing Conditions: VCC = AVCC0 = 2.7 to 5.5 V 32 MHz ≤ PCLKD ≤ 64 MHz Parameter Min Typ Max Unit Test conditions Resolution PCLKD = 64 MHz, DLL Mode = 5-bit mode - 488 - ps - PCLKD = 64 MHz, DLL Mode = 4-bit mode - 976 - ps - PCLKD = 32 MHz, DLL Mode = 5-bit mode - 976 - ps - DNL*1, *2 -5 -LSB - Input capture tGTICW tACYC2 AGTIO, AGTEE (input) tACYC tACKWL tACKWH AGTIO, AGTO, AGTOA, AGTOB (output) ADTRG0 tTRGW KR00 to KR07 tKR |
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