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S3A3 Scheda tecnica(PDF) 87 Page - Renesas Technology Corp |
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S3A3 Scheda tecnica(HTML) 87 Page - Renesas Technology Corp |
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87 / 139 page ![]() R01DS0307EU0100 Rev.1.00 Page 87 of 139 Mar 7, 2017 S3A3 2. Electrical Characteristics Figure 2.63 SPI timing (master, CPHA = 0) (bit rate: PCLKA division ratio is set to 1/2) Figure 2.64 SPI timing (master, CPHA = 1) (bit rate: PCLKA division ratio is set to any value other than 1/2) SSLA0 to SSLA3 output RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output MISOA input MOSIA output LSB IN tDr, tDf tSU tHF tLEAD tTD tLAG tSSLr, tSSLf tOH tOD MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT MSB IN DATA tHF tSU tH tLEAD tTD tLAG tSSLr, tSSLf tOH tOD MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT SSLA0 to SSLA3 output RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output MISOA input MOSIA output tDr, tDf |
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