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TSX711 Scheda tecnica(PDF) 21 Page - STMicroelectronics |
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TSX711 Scheda tecnica(HTML) 21 Page - STMicroelectronics |
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21 / 31 page ![]() TSX711, TSX711A, TSX712 Application information DocID025959 Rev 5 21/31 Figure 35: Test configuration for Riso 5.9 PCB layout recommendations Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance. 5.10 Optimized application recommendation It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help to reduce electromagnetic interference impact. Cload VIN + - VCC+ Riso 10 kΩ VCC- VOUT |
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