R5F564MLGDFP datasheet(71/228 Pages) RENESAS

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R01DS0173EJ0110 Rev.1.10

Page 71 of 228

Oct 24, 2016

RX64M Group

4. I/O Registers

 Longword-size I/O registers

MOV.L #SFR_ADDR, R1

MOV.L #SFR_DATA, [R1]

CMP

[R1].L, R1

;; Next process

If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely

completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary

to read or execute operation for all the registers that were written to.

(3)

Number of Access Cycles to I/O Registers

For the number of I/O register access cycles, refer to Table 4.1, List of I/O Registers (Address Order).

The number of access cycles to I/O registers is obtained by following equation.*1

Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +

Number of divided clock synchronization cycles +

Number of bus cycles for internal peripheral busses 1 to 6

The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.

When peripheral functions connected to internal peripheral bus 2 to 6 or registers for the external bus control unit (except

for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.

The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK

(or FCLK, BCLK) or bus access timing.

In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the

sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will

be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of

access states shown in Table 4.1.

When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the

ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described

on an ICLK basis.

In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided

clock synchronization cycles will be one cycle of BCLK at a maximum. Therefore, one BCLK is added to the number of

access cycles shown in Table 4.1.

Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the instruction fetching

to the external memory or bus access from the different bus master (DMAC or DTC).

(4)

Notes on Sleep Mode and Mode Transitions

During sleep mode or mode transitions, do not write to the registers related to system control (indicated by 'SYSTEM' in

the Module Symbol column in Table 4.1, List of I/O Registers (Address Order)).

(5)

Restrictions in Relation to RMPA and String-Manipulation Instructions

The allocation of data to be handled by RMPA or string-manipulation instructions to I/O registers is prohibited, and

operation is not guaranteed if this restriction is not observed.

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