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R5F564MLGDLC Scheda tecnica(PDF) 115 Page - Renesas Technology Corp

Il numero della parte R5F564MLGDLC
Spiegazioni elettronici  120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory
PDF  228 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F564MLGDLC Scheda tecnica(HTML) 115 Page - Renesas Technology Corp

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R01DS0173EJ0110 Rev.1.10
Page 115 of 228
Oct 24, 2016
RX64M Group
4. I/O Registers
000A 009Ah
USB0
Pipe3 Transaction Counter Register
PIPE3TRN
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 009Ch
USB0
Pipe4 Transaction Counter Enable Register
PIPE4TRE
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 009Eh
USB0
Pipe4 Transaction Counter Register
PIPE4TRN
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00A0h
USB0
Pipe5 Transaction Counter Enable Register
PIPE5TRE
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00A2h
USB0
Pipe5 Transaction Counter Register
PIPE5TRN
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00D0h
USB0
Device Address 0 Configuration Register
DEVADD0
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00D2h
USB0
Device Address 1 Configuration Register
DEVADD1
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00D4h
USB0
Device Address 2 Configuration Register
DEVADD2
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00D6h
USB0
Device Address 3 Configuration Register
DEVADD3
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00D8h
USB0
Device Address 4 Configuration Register
DEVADD4
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00DAh
USB0
Device Address 5 Configuration Register
DEVADD5
16
16
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 00F0h
USB0
PHY Cross Point Adjustment Register
PHYSLEW
32
32
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 0400h
USB
Deep Standby USB Transceiver Control/Pin
Monitoring Register
DPUSR0R
32
32
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 0404h
USB
Deep Standby USB Suspend/Resume Interrupt
Register
DPUSR1R
32
32
9 PCLKB
or more
Frequency with 1 + 9
× (frequency ratio of
ICLK/PCLKB)*5
USBb
000A 0500h
PDC
PDC Control Register 0
PCCR0
32
32
2, 3 PCLKB
2 ICLK
PDC
000A 0504h
PDC
PDC Control Register 1
PCCR1
32
32
2, 3 PCLKB
2 ICLK
PDC
000A 0508h
PDC
PDC Status Register
PCSR
32
32
2, 3 PCLKB
2 ICLK
PDC
000A 050Ch
PDC
PDC Pin Monitor Register
PCMONR
32
32
2, 3 PCLKB
2 ICLK
PDC
000A 0510h
PDC
PDC Receive Data Register
PCDR
32
32
2, 3 PCLKB
2 ICLK
PDC
000A 0514h
PDC
Vertical Capture Register
VCR
32
32
2, 3 PCLKB
2 ICLK
PDC
000A 0518h
PDC
Horizontal Capture Register
HCR
32
32
2, 3 PCLKB
2 ICLK
PDC
000C 0000h
EDMAC
0
EDMAC Mode Register
EDMR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0008h
EDMAC
0
EDMAC Transmit Request Register
EDTRR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0010h
EDMAC
0
EDMAC Receive Request Register
EDRRR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0018h
EDMAC
0
Transmit Descriptor List Start Address Register
TDLAR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0020h
EDMAC
0
Receive Descriptor List Start Address Register
RDLAR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0028h
EDMAC
0
ETHERC/EDMAC Status Register
EESR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0030h
EDMAC
0
ETHERC/EDMAC Status Interrupt Enable Register
EESIPR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0038h
EDMAC
0
ETHERC/EDMAC Transmit/Receive Status Copy
Enable Register
TRSCER
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0040h
EDMAC
0
Missed-Frame Counter Register
RMFCR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0048h
EDMAC
0
Transmit FIFO Threshold Register
TFTR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
Table 4.1
List of I/O Registers (Address Order) (44 / 67)
Address
Module
Symbol Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access Cycles
Related
Function
ICLK
PCLK
ICLK
 PCLK



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