WM8740

Production Data

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PD, Rev 4.4, April 2010

11

In a real application the designer is unlikely to have control of the relative power up sequence of

AVDD and DVDD. Using the POR circuit to monitor VMIDLL ensures a reasonable delay between

applying power to the device and Device Ready.

Figure 5 and Figure 6 show typical power up scenarios in a real system. Both AVDD and DVDD must

be written to. Any writes to the device before Device Ready will be ignored.

Figure 5 shows DVDD powering up before AVDD. Figure 6 shows AVDD powering up before DVDD.

In both cases, the time from applying power to Device Ready is dominated by the charge time of

VMIDLL. In the case where AVDD is powered long before DVDD, thus allowing VMIDL to charge

shown in Figure 7.