CS5490 datasheet(16/57 Pages) CIRRUS

16 / 57 page

CS5490

DS982F3

4.6 High-pass & Phase Matching Filters

Optional high-pass filters (HPF in Figure 6) remove any

DC component from the selected signal paths. Each

power calculation contains a current and voltage

channel. If an HPF is enabled in only one channel, a

phase-matching filter (PMF) should be applied to the

other channel to match the phase response of the HPF.

For AC power measurement, high-pass filters should be

enabled on the voltage and current channels. For

information about how to enable and disable the HPF or

PMF on each channel, refer to Config2 register

descriptions in section 6.6 Register Descriptions on

page 32.

4.7 Digital Integrators

Optional digital integrators (INT in Figure 6) are

implemented on the current channel to compensate for

the 90° phase shift and 20dB/decade gain generated

by the Rogowski coil current sensor. When a Rogowski

coil is used as the current sensor, the integrator (INT)

should be enabled on that current channel. For

information about how to enable and disable the INT on

the current channel, refer to Config2 register

descriptions in section 6.6 Register Descriptions on

page 32.

4.8 Low-rate Calculations

All the RMS and power results come from low-rate cal-

culations by averaging the output word rate (OWR) in-

stantaneous values over N samples, where N is the

value stored in the SampleCount register. The low-rate

interval or averaging period is N divided by OWR

(4000Hz if MCLK = 4.096MHz). The CS5490 provides

two averaging modes for low-rate calculations: Fixed

Number of Sample Averaging mode and Line-cycle

Synchronized Averaging mode. By default, the CS5490

averages with the Fixed Number of Samples Averaging

mode. By setting the AVG_MODE bit in the Config2 reg-

ister, the CS5490 will use the Line-cycle Synchronized

Averaging mode.

4.8.1 Fixed Number of Samples Averaging

N is the preset value in the SampleCount register and

should not be set less than 100. By default, the

SampleCount

4000.

With

MCLK = 4.096 MHz, the averaging period is fixed at

N/4000 = 1 second, regardless of the line frequency.

4.8.2 Line-cycle Synchronized Averaging

When operating in Line-cycle Synchronized Averaging

mode, and when line frequency measurement is

enabled (see section 5.4 Line Frequency Measurement

on page 19), the CS5490 uses the voltage (V) channel

zero crossings and measured line frequency to

automatically adjust N such that the averaging period

will be equal to the number of half line-cycles in the

CycleCount register. For example, if the line frequency

is 51Hz, and the CycleCount register is set to 100, N will

4000

(100/2)/51 = 3921

during

continuous

conversion. N is self-adjusted according to the line

frequency, therefore the averaging period is always

close to the whole number of half line-cycles, and the

low-rate calculation results will minimize ripple and

maximize resolution, especially when the line frequency

varies. Before starting a low-rate conversion in the

Line-cycle

Synchronized

Averaging

mode,

the



Registers

...

APCM

Config 2

IACOFF



IRMS

VRMS

QAVG

PAVG

QOFF



POFF



Inverse

Figure 7. Low-rate Calculations

CS5490 Scheda tecnica(PDF) 16 Page - Cirrus Logic

CS5490 Scheda tecnica(HTML) 16 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Scheda tecnica Scarica

Link URL