WM8215

Production Data

w

PD, Rev 4.3, September 2012

9

Figure 3 One-channel CDS Operation (CDS=1)

Notes:

1.

The relationship between input video signal and sample points is controlled by VSMP and RSMP.

2.

When VSMP is high the input video signal is connected to the Video sampling capacitors.

3.

When RSMP is high the input video signal is connected to the Reset sampling capacitors.

4.

RSMP must not go high before the first falling edge of MCLK after VSMP goes low.

5.

It is required that the falling edge of VSMP should occur before the rising edge of MCLK.

6.

In 1-channel CDS mode it is not possible to have an equally spaced Video and Reset sample points with a 45MHz

MCLK.

7.

Non-CDS operation is also possible; RSMP is not required in this mode but can be used to control input clamping.

Timing constraints between vsmp and mclk remain unchanged for non-CDS operation.

Test Conditions

for 1-channel mode unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period – 2/3 channel mode

1 channel mode

16.6

22.2

ns

MCLK high period – 2/3 channel mode

1 channel mode

6.7

8.3

11.1

ns

MCLK low period – 2/3 channel mode

1 channel mode

6.7

8.3

11.1

ns

RSMP pulse high time

5

ns

VSMP pulse high time

5

ns

RSMP falling to VSMP rising time

0

ns

MCLK rising to VSMP rising time

3

ns

MCLK falling to VSMP falling time

0

ns

MCLK falling to VSMP falling time in 1

channel mode

7

ns

VSMP falling to MCLK rising time

0

ns

1

RSMP rising time

1

ns

3-channel mode pixel period

50

ns

2-channel mode pixel period

33.3

ns