EPF8282AV datasheet(33/61 Pages) ALTERA

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Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Table 9. FLEX 8000 LE Timing Parameters

Note (1)

Symbol

Parameter

tLUT

LUT delay for data-in

tCLUT

LUT delay for carry-in

tRLUT

LUT delay for LE register feedback

tGATE

Cascade gate delay

tCASC

Cascade chain routing delay

tCICO

Carry-in to carry-out delay

tCGEN

Data-in to carry-out delay

tCGENR

LE register feedback to carry-out delay

LE register control signal delay

tCH

LE register clock high time

tCL

LE register clock low time

tCO

LE register clock-to-output delay

tCOMB

Combinatorial delay

tSU

LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or load

LE register hold time after clock

tPRE

LE register preset delay

tCLR

LE register clear delay

Table 10. FLEX 8000 Interconnect Timing Parameters

Note (1)

Symbol

Parameter

tLABCASC

Cascade delay between LEs in different LABs

tLABCARRY

Carry delay between LEs in different LABs

tLOCAL

LAB local interconnect delay

tROW

Row interconnect routing delay,

Note (4)

tCOL

Column interconnect routing delay

tDIN_C

Dedicated input to LE control delay

tDIN_D

Dedicated input to LE data delay,

Note (4)

tDIN_IO

Dedicated input to IOE control delay

Table 11. FLEX 8000 External Reference Timing Characteristics

Note (5)

Symbol

Parameter

tDRR

Note (6)

tODH

Output data hold time after clock,

Note (7)

EPF8282AV Scheda tecnica(PDF) 33 Page - Altera Corporation

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