WM8971LEFLSLASHR datasheet(13/56 Pages) WOLFSON

Il numero della parte	WM8971LEFL/R

Spiegazioni elettronici	STEREO CODEC FOR PORTABLE AUDIO APPLLICATIONS

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Produttore elettronici	WOLFSON [Wolfson Microelectronics plc]

Homepage	http://www.wolfsonmicro.com

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WM8971L

AI Rev 3.0 March 2004

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 System Clock Timing Requirements

Test Conditions

CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,

unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKL

MCLK System clock pulse width low

TMCLKH

MCLK System clock cycle time

TMCLKY

MCLK duty cycle

TMCLKDS

60:40

40:60

Test Conditions

CLKDIV2=1, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data,

unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKL

MCLK System clock pulse width low

TMCLKH

MCLK System clock cycle time

TMCLKY

AUDIO INTERFACE TIMING – MASTER MODE

BCLK

(Output)

ADCDAT

ADCLRC/

DACLRC

(Outputs)

DACDAT

DDA

DHT

DST

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

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