AD9208 datasheet(63/137 Pages) AD

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AD9208

Data Sheet

Rev. 0 | Page 62 of 136

Chip

Application

Layer

Chip

Decimation

Ratio

DDC

Input

Type

DDC

Output

Type

Bandwidth

Per DDC1

No. of Virtual

Converters

Required

Four DDCs

Real

Complex

5% × fS

0x0200 = 0x03 (four DDCs; I/Q selected)

0x0201 = 0x04 (chip decimate by 16)

0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer; 6 dB

gain; variable IF; complex output; HB4 + HB3 + HB2 +

HB1 filters)

0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q

input = ADC Channel A)

0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q

input = ADC Channel A)

0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q

input = ADC Channel B)

0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,

0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW

and POW set as required by application for DDC2

0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,

0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW

and POW set as required by application for DDC3

1 fS is the ADC sample rate.

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