TMS44100, TMS44100P, TMS46100, TMS46100P

4194304-WORD BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS561A – MARCH 1995 – REVISED JUNE 1995

2

POST OFFICE BOX 1443

A0

A1

A2

A3

A4

A5

A6

A7

A8

A10

RAS

CAS

W

D

9

10

11

12

14

15

16

17

18

5

3

24

2

1

30D11/21D0

31D21/21D10

C30 [ROW]

G33 [REFRESH ROW]

34 [PWR DWN]

C31 [COL]

G34

33C32

33,31D

34 EN

A, 32D

A

0

4 194 303

RAM 4096K

× 1

&

A

∇

Q

25

A9

22

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

functional block diagram

A0

A1

A10

16

3

8

10

10

16

16

3

Timing and Control

Column-

Address

Buffers

Row-

Address

Buffers

I/O

Buffers

1 of 16

Selection

Data-

In

Reg.

Data-

Out

Reg.

Column Decode

Sense Amplifiers

R

o

w

D

e

c

o

d

e

16

128K Array

128K Array

128K Array

128K Array

128K Array

128K Array

D

RAS

CAS

W

Q