AD9262

Rev. A | Page 6 of 32

DIGITAL SPECIFICATIONS

All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,

unless otherwise noted.

Table 4.

Parameter1

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVPECL

Differential Input Voltage

Full

0.4

0.8

2

V p-p

Input Common-Mode Range

Full

0.3

0.450

0.5

V

High Level Input Current

Full

−60

+60

μA

Low Level Input Current

Full

−60

+60

μA

Input Resistance

Full

20

kΩ

Input Capacitance

Full

1

pF

LOGIC INPUTS (SCLK)

High Level Input Voltage

Full

1.2

DRVDD + 0.3

V

Low Level Input Voltage

Full

0

0.8

V

High Level Input Current

Full

−50

−75

μA

Low Level Input Current

Full

−10

+10

μA

Input Resistance

Full

30

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUTS (SDIO, CSB, RESET)

High Level Input Voltage

Full

1.2

DRVDD + 0.3

V

Low Level Input Voltage

Full

0

0.8

V

High Level Input Current

Full

−10

+10

μA

Low Level Input Current

Full

+40

+135

μA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

5

pF

DIGITAL OUTPUTS

DRVDD = 3.3 V

Full

3.29

V

Full

3.25

V

Full

0.2

V

Full

0.05

V

DRVDD = 1.8 V

Full

1.79

V

Full

1.75

V

Full

0.2

V

Full

0.05

V