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LT1716

1716f

APPLICATIO S I FOR ATIO

The LT1716 comparator features low power operation

with exceptional input precision with rail-to-rail input and

output swing. The comparator operates flawlessly even

when the inputs are pulled over the positive rail or below

the negative rail.

Supply Voltage

The LT1716 operates from 2.7V to 44V. The comparator

can be shut down by removing V+. In this condition, the

input bias current is typically less than 3nA, even if the

inputs are 44V above the negative supply. The LT1716 is

protected against reverse battery voltages of up to 20V.

The reverse battery current is resistive as shown in the

reverse supply current graph.

Inputs

The comparator inputs can swing from 0.5V above to 44V

above V–. If one input is within this range, the other input

can be forced up to 5V below V– without phase reversal

occuring at the output.

The LT1716 has three stages—NPN, PNP and common

base (see Simplified Schematic)—resulting in three dis-

tinct operating regions and two transition regions as

shown in the Input Bias Current vs Common Mode typical

performance curve.

For input voltages about 0.8V or more below V+, the PNP

input stage is active and the input bias current is typically

– 4nA. The PNP differential input stage will have bias

current that flows out of the device. With a differential

input voltage of even just 100mV or so, there will be zero

bias current into the higher of the two inputs, while the

current flowing out of the lower input will be twice the

measured bias current.

When the input voltage is about 0.5V or less from V+, the

NPN state is operating and the input bias current is

typically 10nA. Increases in temperature will cause the

voltage at which operation switches from the PNP stage to

the NPN stage to move towards V+. The input offset

voltage of the NPN stage is untrimmed and is typically

500

µV.

A Schottky diode in the collector of each NPN transistor of

the NPN input stage allows the LT1716 to operate with

either or both of its inputs above V+. At about 0.3V above

V+, the NPN transistor is fully saturated and the input bias

current is typically 4

µA at room temperature. The input

offset voltage is typically 500

µV when operating above V+.

The LT1716 will operate with its input 44V above V –,

regardless of V+.

The transition to the negative common mode input stage

occurs at 0.3V above V –. Above this trip point the PNP

stage is active. When the inputs are 0.3V below V –, the

common base input stage is active in addition to the PNP

stage. The input bias current out of each input becomes

VIN/5kΩ. The LT1716 is designed to operate when either

input falls below the negative supply. Internal resistors

protect the inputs for faults below the negative supply of

up to 5V without phase reversal. The built-in 5k resistor

limits the current at each input to 1mA at 5V below the

negative supply. External matched input resistors can be

added for increased voltage fault operation below the

negative supply but the maximum input current should be

kept under 1mA.

Input Protection

The inverting and noninverting input pins of the LT1716

have on-chip protection. ESD protection is provided to

prevent damage during handling. The input transistors

have voltage clamping and limiting resistors to protect

against excursions as much as 5V below V – . There are no

clamping diodes between the inputs and the maximum

differential input voltage is 44V.

Output

The output stage of the LT1716 can drive loads connected

to a supply more positive than the device, the same as

comparators with open collector output stages. The out-

put of the LT1716 can be pulled up to 44V above V –,

regardless of V+.

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