AC08FSM datasheet(183/223 Pages) TECCOR

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Application Notes

AN1008

AN1008 - 5

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Thyristor Product Catalog

+1 972-580-7777

Figure AN1008.9

Typical Triac Latching (IL) Requirements for Four

Quadrants versus Gate Current (IGT)

IH: Holding Current — SCR and Triac

The holding current is the DC principal on-state current below

which the device will not stay in regeneration/on state after latch-

ing and gate signal is removed. This current is equal to or lower

in value than the latching current (Figure AN1008.1 and Figure

AN1008.2) and is related to and has the same temperature

dependence as the DC gate trigger current shown in Figure

AN1008.10. Both minimum and maximum holding current may be

important. If the device is to stay in conduction at low-anode cur-

rents, the maximum holding current of a device for a given circuit

must be considered. The minimum holding current of a device

must be considered if the device is expected to turn off at a low

DC anode current. Note that the low DC principal current condi-

tion is a DC turn-off mode, and that an initial on-state current

(latching current) is required to ensure that the thyristor has been

fully turned on prior to a holding current measurement.

Figure AN1008.10

Normalized DC Holding Current versus

Case Temperature

dv/dt, Static: Critical Rate-of-rise of Off-state Voltage —

SCR and Triac

Static dv/dt is the minimum rate-of-rise of off-state voltage that

a device will hold off, with gate open, without turning on.

Figure AN1008.11 illustrates the exponential definition. This

value will be reduced by a positive gate signal. This charac-

teristic is temperature-dependent and is lowest at the maxi-

mum-rated junction temperature. Therefore, the characteristic

is determined at rated junction temperature and at rated

forward off-state voltage which is also a worst-case situation.

Line or other transients which might be applied to the thyristor

in the off state must be reduced, so that neither the rate-of-

rise nor the peak voltage are above specifications if false firing

is to be prevented. Turn-on as result of dv/dt is non-destructive

as long as the follow current remains within current ratings of

the device being used.

Figure AN1008.11

Exponential Rate-of-rise of Off-state Voltage

Defining dv/dt

dv/dt, Commutating: Critical Rate-of-rise of

Commutation Voltage — Triac

Commutating dv/dt is the rate-of-rise of voltage across the main

terminals that a triac can support (block without switching back

on) when commutating from the on state in one half cycle to the

off state in the opposite half cycle. This parameter is specified at

maximum rated case temperature (equal to TJ) since it is temper-

ature-dependent. It is also dependent on current (commutating

di/dt) and peak reapplied voltage (line voltage) and is specified at

rated current and voltage. All devices are guaranteed to commu-

tate rated current with a resistive load at 50 Hz to 60 Hz. Com-

mutation of rated current is not guaranteed at higher frequencies,

and no direct relationship can be made with regard to current/

temperature derating for higher-frequency operation. With induc-

tive loading, when the voltage is out of phase with the load cur-

rent, a voltage stress (dv/dt) occurs across the main terminals of

the triac during the zero-current crossing. (Figure AN1008.12) A

snubber (series RC across the triac) should be used with induc-

tive loads to decrease the applied dv/dt to an amount below the

minimum value which the triac can be guaranteed to commutate

off each half cycle.

III

1.0

2.0

3.0

4.0

5.0

6.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

IGT — mA

1.0

2.0

3.0

4.0

-65

-15

+65

+25

+125

-40

Case Temperature (TC) – ˚C

INITIAL ON-STATE CURRENT

= 400 mA dc

Critical dv/dt

= 0.63

t = RC

63% of VD

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