THS1040

SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004

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PRINCIPLES OF OPERATION

functional overview

See the functional block diagram. A single-ended, sample rate clock is required at pin CLK for device operation.

Analog inputs AIN+ and AIN− are sampled on each rising edge of CLK in a switched capacitor sample and hold

unit, the output of which feeds the ADC core, where analog-to-digital conversion is performed against the ADC

reference voltages REFT and REFB.

Internal or external ADC reference voltage configurations are selected by connecting the MODE pin

appropriately. When MODE = AGND, the user must provide external sources at pins REFB and REFT. When

and REFB pins using the voltage at pin VREF as its input. The user can choose to drive VREF from the internal

bandgap reference, or disable A1 and provide their own reference voltage at pin VREF.

On the fourth rising CLK edge following the edge that sampled AIN+ and AIN−, the conversion result is output

via data pins D0 to D9. The output buffers can be disabled by pulling pin OE high.

The following sections explain further:

set the ADC input range and hence the input range at AIN+ and AIN−.

to match the device input range to the input signal.

signal processing chain (sample and hold, ADC)

Figure 20 shows the signal flow through the sample and hold unit to the ADC core.

Sample

and

Hold

X1

X−1

ADC

Core

VQ+

VQ−

REFT

REFB

AIN+

AIN−

Figure 20. Analog Input Signal Flow