AD7314ARMZ datasheet(3/9 Pages) AD

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REV. A

–2–

AD7314–SPECIFICATIONS*(T

A = TMIN to TMAX, VDD = 2.65 V to 5.5 V, unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TEMPERATURE SENSOR AND ADC

Accuracy

±2.0

∞CTA = –35∞C to +85∞C. VDD = 2.65 V to 2.9 V

±1.0

∞CTA = –35∞C to +85∞C. VDD = 3 V to 5.5 V

Resolution

Bits

Update Rate, tR

400

Temperature Conversion Time

SUPPLIES

Supply Voltage

2.65

5.5

For Specified Performance

Supply Current

Normal Mode (Inactive)

250

300

Part Not Converting, VDD = 2.65 V to 2.9 V

275

Part Not Converting, VDD = 3 V to 5.5 V

Normal Mode (Active)

Part Converting, VDD = 2.65 V to 2.9 V

1.2

Part Converting, VDD = 3 V to 5.5 V

Shutdown Mode

mAVDD = 2.65 V to 2.9 V

mAVDD = 3 V to 5.5 V

Power Dissipation

860

mWVDD = 2.65 V. Using Normal Mode

(Auto Conversion)

Power Dissipation

VDD = 2.65 V. Using Shutdown Mode

1 SPS

10 SPS

3.3

100 SPS

DIGITAL INPUT

Input High Voltage, VIH

1.85

VDD = 2.65 V to 2.9 V

Input Low Voltage, VIL

0.53

VDD = 2.65 V to 2.9 V

Input High Voltage, VIH

2.4

VDD = 3 V to 5.5 V

Input Low Voltage, VIL

0.8

VDD = 3 V to 5.5 V

Input Current, IIN

±1

mAVIN = 0 V to VDD

Input Capacitance, CIN

All Digital Inputs

DIGITAL OUTPUT

Output High Voltage, VOH

2.4

ISOURCE = ISINK = 200

Output Low Voltage, VOL

0.4

IOL = 200

Output Capacitance, COUT

*All specifications apply for –35

∞C to +85∞C, unless otherwise noted.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1, 2

Parameter

Limit

Unit

Comments

ns min

CE to SCLK Setup Time

ns min

SCLK High Pulse Width

ns min

SCLK Low Pulse Width

ns max

Data Access Time after SCLK Rising Edge

ns min

Data Setup Time prior to SCLK Falling Edge

ns min

Data Hold Time after SCLK Falling Edge

ns min

CE to SCLK Hold Time

ns max

CE to SDO High Impedance

NOTES

1Guaranteed by design and characterization, not production tested.

2All input signals are specified with tr = tf = 5 ns (10% to 90% of V

DD) and are timed from a voltage level of 1.6 V.

3All specifications apply for –35

∞C to +85∞C, unless otherwise noted.

4Measured with the load circuit of Figure 2.

Specifications subject to change without notice.

(TA

3 = T

MIN to TMAX, VDD = 2.65 V to 5.5 V, unless otherwise noted. See Figure 1.)

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