SN74AVC1T45DBVR datasheet(2/22 Pages) TI

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

DIR

VCCA

VCCB

SN74AVC1T45

SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER

WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SCES530D – DECEMBER 2003 – REVISED NOVEMBER 2005

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of

the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data

from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the

A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic

HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance

state.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

FUNCTION TABLE(1)

INPUT

OPERATION

DIR

B data to A bus

A data to B bus

(1)

Input circuits of the data I/Os

always are active.

LOGIC DIAGRAM (POSITIVE LOGIC)

SN74AVC1T45DBVR Scheda tecnica(PDF) 2 Page - Texas Instruments