AD9869BCPZ datasheet(12/37 Pages) AD

12 / 37 page

AD9869

Rev. A | Page 11 of 36

Pin No.

Mnemonic

Mode1

Description

TXCLK

ADIO Sample Clock Input.

TXQUIET

Fast TxDAC/IAMP Power-Down.

RXCLK

ADIO Request Clock Input.

Rx and Tx Clock Output at 2 x fADC.

17, 64

DRVDD

Digital Output Driver Supply Input.

18, 63

DRVSS

Digital Output Driver Supply Return.

CLKOUT1

fADC/N Clock Output (R = 1, 2, or 3).

SDIO

Serial Port Data Input/Output.

SDO

Serial Port Data Output.

SCLK

Serial Port Clock Input.

SEN

Serial Port Enable Input.

GAIN

Tx Data Port (Tx[5:0]) Mode Select.

PGA[5]

HD or FD

MSB of PGA Input Data Port.

25 to 29

PGA[4:0]

HD or FD

Bit 4 to Bit 0 of PGA Input Data Port.

RESET

Reset Input (Active Low).

31, 34, 36, 39, 44, 47, 48

AVSS

Analog Supply Return.

32, 33

REFB, REFT

ADC Reference Decoupling Nodes.

35, 40, 43

AVDD

Analog Power Supply Input.

37, 38

RX−, RX+

Receive Path − and + Analog Inputs.

REFADJ

TxDAC Full-Scale Current Adjust.

REFIO

TxDAC Reference Input/Output.

45, 49

Do Not Connect; Leave Open.

IOUTN−

−Tx Mirror Current Output Sink.

IOUTN+

+Tx Mirror Current Output Sink.

IOUTP−

−TxDAC Current Output Source.

IOUTP+

+TxDAC Current Output Source.

MODE

Digital Interface Mode Select Input, Low = HD, High = FD.

CONFIG

Power-Up SPI Register Default Setting Input.

CLKVSS

Clock Oscillator/Synthesizer Supply Return.

XTAL

Crystal Oscillator Inverter Output.

OSCIN

Crystal Oscillator Inverter Input.

CLKVDD

Clock Oscillator/Synthesizer Supply.

DVSS

Digital Supply Return.

DVDD

Digital Supply Input.

CLKOUT2

fOSCIN/L Clock Output (L = 1, 2, or 4).

PWRDWN

Power-Down Input.

EPAD

The exposed pad must be soldered to ground.

1 HD = half-duplex mode; FD = full-duplex mode.

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