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AD2S1200YST Scheda tecnica(PDF) 16 Page - Analog Devices |
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AD2S1200YST Scheda tecnica(HTML) 16 Page - Analog Devices |
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16 / 25 page ![]() AD2S1200 Rev. 0 | Page 15 of 24 t11 tSCLK t10 t9 t8 SCLK SO MSB MSB–1 LSB RDVEL DOS LOT PAR RD t3 t6 t7 tCK CLKIN SO VEL POS t2 SAMPLE CS RD RDVEL t1 t1 t3 t5 t4 t5 t4 t7 t6 Figure 8. Serial Port Read Timing Table 6. Serial Port Timing Parameter Description Min Typ Max t8 MSB Read Time from RD/CS to SCLK 15 ns tSCLK t9 Enable Time RD/CS to DB Valid 12 ns t10 Delay SCLK to DB Valid 14 ns t11 Disable Time RD/CS to DB High Z 18 ns tSCLK Serial Clock Period (25 MHz Max) 40 ns |
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