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THCV233 Scheda tecnica(PDF) 6 Page - THine Electronics, Inc. |
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THCV233 Scheda tecnica(HTML) 6 Page - THine Electronics, Inc. |
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6 / 34 page ![]() Pin Name Pin # Type* Description RLA -/+ 24,23 LO RLB -/+ 22,21 LO RLC -/+ 20,19 LO RLCLK -/+ 18,17 LO RLD -/+ 16,15 LO RLE -/+ 14,13 LO RX0N/P 40,41 CI RX1N/P 44,45 CI LOCKN 38 OD Lock detect output (LOCKN). It must be connected to Tx LOCKN with a Tx side10kΩ pull-up resistor. LOCKN is output only. HTPDN 37 OD Hot plug detect output (HTPDN). It must be connected to Tx HTPDN with a Tx side 10kΩ pull-up resistor. HTPDN is output only. Reserved [1,2] 2,3 - It must be open. Reserved [5] 8 - It must be connected with a pull-up resistor to 3.3V. DEOUT 9 O DE signal output (DEOUT) for LVDS data sets. When used as DEOUT, no external component is required. It is push pull output. DEOUT output DE timing depending upon data stream state. DEOUT is output only. Bit Error Test (BET) result output under Field-BET operation H : No error, L : Bit error occured DGLOCK 36 BPU Multiple-chip configuration total Rx side LOCKN indicator (DGLOCK). When used as DGLOCK, it is internally connected with a pull-up resistor to 3.3V. No external component is required. LOCKN arrange among Rx Multiple-chip configuration is achieved by connecting all DGLOCK pins. Reserved [0,3,4,6,7,8,9] 1,4,5,27, 28,33,34 - It must be connected to GND. MODE [1:0] 29,30 I Operation mode select input. MODE [1:0] =LL : Dual-in/Selected single-out (Lane0) =LH : Dual-in/Single-out =HL : Dual-in/Selected single-out (Lane1) =HH : Single-in/Single-out PDN 35 I Power down Schmitt input. H: Normal operation, L: Power down RS 32 I LVDS output swing range select input. H : Normal swing (350mv@typ.), L : Reduced swing (200mv@typ.) Latch select input under Field-BET operation H : Latched result, L : NOT Latched result COL 10 I Data width setting for High Speed CML signal output. H : 24bit, L : 32bit BET 48 I Field-BET entry. H : Field BET Operation, L : Normal Operation LAVDH 12,25 P33 LVDS power supply (3.3V) LAGND 11,26 GND LVDS GND CAVDL 42,47 P18 High-speed signal analog power supply (1.8V) CAGND 39,43,46 GND High-speed signal analog GND VDD 6,31 P18 Logic power supply (1.8V) VSS 7 GND Logic GND EXPGND 49 GND Exposed PAD GND LVDS signal output. High-speed CML signal input. |
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