M95256-RBN6TG datasheet(16/39 Pages) STMICROELECTRONICS

Il numero della parte	M95256-RBN6TG

Spiegazioni elettronici	256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock

PDF	39 Pages

Scroll/Zoom	100%

Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

Homepage	http://www.st.com

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16 / 39 page

M95256, M95128

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(BP1, BP0) bits of the Status Register, are

also hardware protected against data

modification.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be entered:

–

by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W) Low

–

or by driving Write Protect (W) Low after

setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Block Protect (BP1, BP0) bits of

the Status Register, can be used.

Figure 11. Write Status Register (WRSR) Sequence

AI02282D

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

M95256-RBN6TG Scheda tecnica(PDF) 16 Page - STMicroelectronics