AD7623AST datasheet(7/29 Pages) AD

7 / 29 page

AD7623

Rev. 0 | Page 6 of 28

SERIAL CLOCK TIMING SPECIFICATIONS

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

DIVSCLK[0]

Symbol

Unit

SYNC to SCLK First Edge Delay Minimum

t18

0.5

Internal SCLK Period Minimum

t19

Internal SCLK Period Maximum

t19

100

Internal SCLK High Minimum

t20

Internal SCLK Low Minimum

t21

SDOUT Valid Setup Time Minimum

t22

SDOUT Valid Hold Time Minimum

t23

0.5

SCLK Last Edge to SYNC Delay Minimum

t24

0.5

BUSY High Width Maximum

t28

0.780

1.000

1.440

2.320

μs

NOTE

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

SDOUT ARE DEFINED WITH A MAXIMUM LOAD.

CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

500

μAI

500

μAI

1.4V

TO OUTPUT

50pF

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, CL = 10 pF

0.8V

tDELAY

Figure 3. Voltage Reference Levels for Timing

AD7623AST Scheda tecnica(PDF) 7 Page - Analog Devices

AD7623AST Scheda tecnica(HTML) 7 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Scheda tecnica Scarica

Link URL