AD7667AST datasheet(24/29 Pages) AD

24 / 29 page

AD7667

Rev. 0 | Page 23 of 28

MASTER SERIAL INTERFACE

Usually, because the AD7667 is used with a fast throughput, the

Master Read During Conversion mode is the most recommen-

ded serial mode. In this mode, the serial clock and data toggle at

appropriate instants, minimizing potential feedthrough between

digital activity and critical conversion decisions.

Internal Clock

The AD7667 is configured to generate and provide the serial

data clock SCLK when the EXT/INT pin is held LOW. The

AD7667 also generates a SYNC signal to indicate to the host

when the serial data is valid. The serial clock SCLK and the

SYNC signal can be inverted if desired. Depending on the

RDC/SDIN input, the data can be read after each conversion or

during the following conversion. Figure 39 and Figure 40 show

detailed timing diagrams of these two modes.

In Read After Conversion mode, it should be noted that unlike

in other modes, the BUSY signal returns LOW after the 16 data

bits are pulsed out and not at the end of the conversion phase,

which results in a longer BUSY width.

BUSY

SYNC

SCLK

SDOUT

t28

t29

t14

t18

t19

t20

t21

t24

t26

t27

t23

t22

t16

t15

D15

D14

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

t25

t30

CNVST

CS, RD

EXT/INT = 0

Figure 39. Master Serial Data Timing for Reading (Read after Convert)

EXT/INT = 0

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

t17

t14

t19

t20 t21

t24

t26

t25

t27

t23

t22

t16

t15

D15

D14

BUSY

SYNC

SCLK

SDOUT

CNVST

CS, RD

Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

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