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AD7992

Rev. 0 | Page 20 of 28

SERIAL INTERFACE

Control of the AD7992 is carried out via the I2C-compatible

serial bus. The AD7992 is connected to this bus as a slave device

under the control of a master device, such as the processor.

SERIAL BUS ADDRESS

Like all I2C-compatible devices, the AD7992 has a 7-bit serial

address. The 3 MSBs of this address for the AD7992 are set to

010. The device comes in two versions, the AD7992-0 and the

AD7992-1. The two versions have three different I2C addresses

available, which are selected by either tying the address select

pin, AS, to AGND or VDD, or by letting the pin float (refer to

Table 6). By giving different addresses for the two versions, up

to five AD7992 devices can be connected to a single serial bus,

or the addresses can be set to avoid conflicts with other devices

on the bus.

The serial bus protocol operates as follows.

The master initiates data transfer by establishing a START

condition, defined as a high-to-low transition on the serial

data line SDA, while the serial clock line, SCL, remains high.

This indicates that an address/data stream follows. All slave

peripherals connected to the serial bus respond to the START

condition and shift in the next eight bits, consisting of a 7-bit

address (MSB first) plus an R/W bit that determines the

direction of the data transfer—that is, whether data is written to

or read from the slave device.

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the low

period before the ninth clock pulse, known as the acknowledge

bit. All other devices on the bus remain idle while the selected

device waits for data to be read from or written to it. If the R/W

bit is a 0, the master writes to the slave device. If the R/W bit is

a 1, the master reads from the slave device.

Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an acknowledge bit from

the receiver of data. Transitions on the data line must occur

during the low period of the clock signal and remain stable

during the high period, because a low-to-high transition when

the clock is high may be interpreted as a STOP signal.

When all data bytes have been read or written, stop conditions

are established. In write mode, the master pulls the data line

high during the 10th clock pulse to assert a STOP condition. In

read mode, the master device pulls the data line high during the

low period before the ninth clock pulse. This is known as no

acknowledge. The master then takes the data line low during

the low period before the 10th clock pulse, then high during the

10th clock pulse to assert a STOP condition.

Any number of bytes of data may be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

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