IFPA300, IFPA301

Monolithic JFET Preamplifier

Input FET J1 selected to the

following elecrical parameters.

Parameter

Conditions

Min

Max

Units

Vds = 0, Ig = 1 µA

– 25

Volts

Vds = 0, Vgs = – 10 V

2

nA

Vds = 0, Vgs = 10 V

40

500

mA

Vds = 0, Id = 1 µA

1

2

Volts

Vgs = 0, Vds = 10 V

50

mM

Id = 1 µA

0.35

0.65

Volts

Test Circuit Reference

Parameter

Conditions

Min

Max

Units

VDCout

Vdd = 12 V, – VS = – 6 V

6

10

V

Test pt #1

Vin

Vdd = 12 V, – VS = – 6 V

– 0.6

– 1.6

V

Test pt #2

VACout

Vdd = 12 V, – VS = – 6 V

50

mV

t = O µsec

VACout

Vdd = 12 V, – VS = – 6 V

20

mV

t = 100 µsec

IFPA300 uses TO-99 Package

Dimensions in Inches (mm)

Pin Configuration

1 Bias 3, 2 VSS, 3 Bias 1, 4 VDD /Substrate

5 Open Drain Output, 6 Open Source Output, 7 Bias 2, 8 Input

IFPA301 uses SOIC-8 Package

Dimensions in Inches (mm)

Pin Configuration

1 Bias 2, 2 Input, 3 Bias 3, 4 VSS, 5 Bias 1, 6 VDD/Substrate

7 Open Drain Output, 8 Open Source Output

01/99

xi

1000 N. Shiloh Road, Garland, TX 75042

www.interfet.com

Test Point #

Test Point #2

DUT

J5

J6

J7

J1

J2

J3

J4

J8

VSS

VDD

VDD = +12 V

– Vsupply = – 6 V

Open

Substrate

Source

Output

Open

Drain

Output

120K

20K

10K

Ω

Bias 1

Bias 2

Bias 3

Input

2M

Ω

1M

Ω

AC

Input

10pF

10pF

0.009 (0.23)

0.007 (0.18)

45

°

0.022 (0.56)

0.018 (0.046

0.158 (4.01)

0.150 (3.81)

0.244 (6.20)

0.228 (5.79)

0.028 (0.71)

0.024 (0.61)

0.050 (1.27)

0.015 (0.37)

Min.

0.018 (0.46

0.014 (0.36)

0.197 (5.00)

0.188 (4.78)

0.049 (1.24)

0.059 (1.50)

0.069 (1.75)

0.053 (1.35)

5

6

Top

7

8

4

3

2

1

45

°

6

2

31

48

57

0.010 (0.25)

0.040 (1.02)

Bottom View

8 Leads - Dia.

0.016 (0.41)

0.021 (0.53)

0.335 (8.51)

0.370 (9.40)

0.110 (2.79)

0.160 (4.06)

0.500 (12.70)

0.305 (7.75)

0.335 (8.51)

0.028 (0.71)

0.034 (0.86)

0.200 (5.08)

Basic

0.029 (0.74)

0.045 (1.14)

0.010 (0.25)

0.040 (1.02)

Standoff

0.165 (4.19)

0.185 (4.70)

Databook.fxp

1/13/99 2:09 PM

Page xi