| Produttore elettronici | Il numero della parte | Scheda tecnica | Spiegazioni elettronici |
 Cypress Semiconductor |
CY7C2245KV18
|
841Kb/28P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
|
|
CY7C2245KV18-450BZXI
|
841Kb/28P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
|
 List of Unclassifed Man... |
CY7C225-30PC
|
34Kb/2P |
C-MOS 4K (512X8)-BIT PROM WITH REGISTER
|
 Cypress Semiconductor |
CY7C225A
|
186Kb/9P |
512 x 8 Registered PROM
|
|
CY7C225A-25PC
|
186Kb/9P |
512 x 8 Registered PROM
|
|
CY7C225A-25PC
|
322Kb/10P |
512 x 8 Registered PROM
|
|
CY7C225A-30JC
|
186Kb/9P |
512 x 8 Registered PROM
|
|
CY7C225A-40LMB
|
186Kb/9P |
512 x 8 Registered PROM
|
|
CY7C225A
|
322Kb/10P |
512 x 8 Registered PROM
|
|
CY7C2262XV18
|
478Kb/29P |
36-Mbit QDR짰 II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2263KV18
|
910Kb/32P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2263KV18-450BZXI
|
910Kb/32P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2263KV18-550BZXC
|
910Kb/32P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2263KV18-550BZXI
|
910Kb/32P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2263XV18
|
1Mb/29P |
36-Mbit QDR짰 II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2264XV18
|
478Kb/29P |
36-Mbit QDR짰 II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2265KV18
|
910Kb/32P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2265KV18-400BZXI
|
910Kb/32P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2265KV18-450BZC
|
910Kb/32P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
|
CY7C2265KV18-550BZXC
|
910Kb/32P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|