The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications.
The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to output the complete complex (32132) bit result within a single cycle. The data format is fractional two’s complement.

FEATURES
■ Complex Number (16116)3(16116) Multiplication
■ Full 32-bit Result
■ 20MHz Clock Rate
■ Block Floating Point FFT Butterfly Support
■ (21)3(21) Trap
■ Two’s Complement Fractional Arithmetic
■ TTL Compatible I/O
■ Complex Conjugation
■ 2 Cycle Fall Through
■ 144-pin PGA or QFP packages

APPLICATIONS
■ Fast Fourier Transforms
■ Digital Filtering
■ Radar and Sonar Processing
■ Instrumentation
■ Image Processing