PDSP16116 datasheet(2/17 Pages) MITEL

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PDSP16116

SYSTEM FEATURES

The PDSP16116 has a number of features tailored for sys-

tem applications.

(21)3(21) Trap

In multiply operations using two’s complement fractional no-

tation, the (21)3(21) operation forms an invalid result because

11 is not representable in the fractional number range. The

PDSP16116 eliminates this problem by trapping the (21)3(21)

operation and forcing the multiplier result to become the most

positive representable number.

Complex Conjugation

Many algorithms using complex arithmetic require conjuga-

tion of complex data stream. This operation has traditionally re-

quired an additional ALU to multiply the imaginary component

by -1. The PDSP16116 eliminates this requirement by offering

on-chip complex conjugation of either of the two incoming com-

plex data words with no loss in throughput.

Easy Interfacing

As with all PDSP family members the PDSP16116 has reg-

istered l/O for data and control. Data inputs have independent

clock enables and data outputs have independent three state

output enables.

Signal

XR15:0

Xl15:0

YR15:0

Yl15:0

PR15:0

Pl15:0

CLK

CONX

CONY

ROUND

MBFP

AR15:1 3

Al15:1 3

WTA1:0

WTB1:0

WTOUT1:0

SFTA1:0

SFTR2:0

GWR4:0

OSEL1:0

VDD

GND

Type

Input

Output

Input

Output

Input

Power

Description

16-bit input for real X data

16-bit input for imaginary X data

16-bit input for real Y data

16-bit input for imaginary Y data

16-bit output for real P data

16-bit output for imaginary P data

Clock; new data is loaded on rising edge of CLK

Clock, enable X-port input register

Clock, enable Y-port input register

Conjugate X data

Conjugate Y data

Rounds the real and imaginary results

Mode select (BFP/Normal)

Start of BFP operations (see Note 1)

End of pass (See Note 1)

3 MSBs from real part of A-word (See Note 1)

3 MSBs from imaginary part of A-word (See Note 1)

Word tag from A-word

Word tag from B-word/shift control (See Note 2)

Word tag output (See Note 1)

Shift control for A-word / overflow flag (See Note 2)

Shift control for accumulator result (See Note 1)

Global weighting register contents (See Note 1)

Selects the desired output configuration

Output enables

15V Supply (See Note 3)

0V Supply (See Note 3)

Normal

mode

configuration

Tie low

NOTES

1. Used only in BFP mode

2. Performs different functions in BFP/Normal modes

3. All supply pins must be connected

Table 1 Signal descriptions

CEX

CEY

SOBFP

EOPSS

OER, OEI

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