HT48C06 datasheet(13/38 Pages) HOLTEK

13 / 38 page

HT48R05A-1/HT48C05/HT48R06A-1/HT48C06

Rev. 1.10

June 9, 2004

Timer/Event Counter

A timer/event counter (TMR) is implemented in the

microcontroller. The timer/event counter contains an 8-bit

programmable count-up counter and the clock may come

from an external source or the system clock.

Using external clock input allows the user to count exter-

nal events, measure time internals or pulse widths, or

generate an accurate time base. While using the inter-

nal clock allows the user to generate an accurate time

base.

The timer/event counter can generate PFD signal by us-

ing external or internal clock and PFD frequency is de-

termine by the equation fINT/[2

´(256-N)].

There are 2 registers related to the timer/event counter;

TMR ([0DH]), TMRC ([0EH]). Two physical registers are

mapped to TMR location; writing TMR makes the start-

ing value be placed in the timer/event counter preload

timer/event counter. The TMRC is a timer/event counter

control register, which defines some options.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the fINT clock. The

pulse width measurement mode can be used to count

the high or low level duration of the external signal

(TMR). The counting is based on the fINT clock.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFH. Once over-

flow occurs, the counter is reloaded from the timer/event

counter preload register and generates the interrupt re-

quest flag (TF; bit 5 of INTC) at the same time.

In the pulse width measurement mode with the TON

and TE bits equal to one, once the TMR has received a

transient from low to high (or high to low if the TE bits is

²0²) it will start counting until the TMR returns to the orig-

inal level and resets the TON. The measured result will

remain in the timer/event counter even if the activated

Label

(TMRC)

Bits

Function

PSC0~PSC2

0~2

To define the prescaler stages, PSC2, PSC1, PSC0=

000: fINT=fSYS/2

001: fINT=fSYS/4

010: fINT=fSYS/8

011: fINT=fSYS/16

100: fINT=fSYS/32

101: fINT=fSYS/64

110: fINT=fSYS/128

111: fINT=fSYS/256

To define the TMR active edge of the timer/event counter

(0=active on low to high; 1=active on high to low)

TON

To enable or disable timer counting

(0=disabled; 1=enabled)

Unused bit, read as

²0²

TM0

TM1

To define the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMRC Register

T M 1

T M 0

T M R

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

T i m e r / E v e n t

C o u n t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

1 / 2

B Z

8 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

P S C 2 ~ P S C 0

Timer/Event Counter

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