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S70FS01GS Scheda tecnica(PDF) 32 Page - Cypress Semiconductor |
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S70FS01GS Scheda tecnica(HTML) 32 Page - Cypress Semiconductor |
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32 / 141 page ![]() S70FS01GS Document Number: 002-03833 Rev. *C Page 32 of 141 Notes: 1. IO3 / RESET# Low is ignored during Power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine when CS# may go Low. 2. If Quad mode is enabled, IO3 / RESET# Low is ignored during tCS 3. Sum of tRP and tRH must be equal to or greater than tRPH. Figure 5.7 Hardware Reset when Quad Mode is not enabled and IO3 / Reset# is Enabled Figure 5.8 Hardware Reset when Quad Mode and IO3 / Reset# are Enabled Table 5.3 Hardware Reset Parameters Parameter Description Limit Time Unit tRS Reset Setup - Prior Reset end and RESET# high before RESET# low Min 50 ns tRPH Reset Pulse Hold - RESET# low to CS# low Min 35 µs tRP RESET# Pulse Width Min 200 ns tRH Reset Hold - RESET# high before CS# low Min 50 ns IO3_RESET# CS# Any prior reset tRS tRP tRH tRH tRPH tRPH IO3_RESET# CS# Reset Pulse Prior access using IO3 for data tRP tRH tRPH tCS tDIS |
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